\section{Background}

Before delving into the details of the HiPerCopS IDE, it is important to understand the context and current state of the HiPerCopS hardware architecture. This section will explain the unique features of the architecture and the work that has been done up to this point. This background information was the fundamental driving force behind many of the decisions made during the development of the IDE.

\subsection{Computers and their Applications}

Computing devices are designed with specific applications in mind. For example, battery-powered mobile devices need processors that feature low power consumption. A typical coffee maker does not require top-of-the-line microprocessor technology, just a simple integrated circuit that can control the brewing process. In computer engineering, the rule is that the target application should specify the hardware requirements.

These days, computers are used in countless applications. In fact, it is difficult to identify an area of society that has not been affected by a digital device. With this ubiquity and pervasiveness, it is easy to imagine the diversity among the specific applications of computer technology. Each application has a unique set of requirements, and each set of requirements can be satisfied by a specific type of computing device. It makes sense, then, that the number of device types is proportional to the number of applications.

\subsection{Hardware Architecture Classification}

To organize this large field of digital technology, computer systems are usually grouped according to hardware architecture. Hardware architecture refers to the physical properties of the system components, how they are arranged, and how they interact with each other. There are four major categories of hardware architecture: application-specific integrated circuits (ASICs), reconfigurable hardware, digital signal processors (DSPs), and general purpose processors.

ASICs are typically small and inexpensive. Each ASIC is designed to perform a specific function with limited scope. This makes the architecture an ideal choice for embedded devices and simple consumer electronics.

Reconfigurable hardware is unique because it can be manipulated to perform a number of different tasks. Other hardware architecture categories are limited to a fixed structure, but the fundamental execution paths of reconfigurable devices can be altered to modify their behavior.

Digital signal processors are designed to handle multimedia data. They can be used to capture, encode, communicate, and decode digital signals such as images, video, and sound. The algorithms involved in these processes can be quite complex, so specialized hardware is needed to perform these tasks.

General purpose processors are found in a variety of applications. They are able to implement nearly any solution, and are found in modern PCs. Members of this class of hardware architecture are usually more expensive, due to the wide range of operations that they can perform.

\begin{figure}
\centering
\includegraphics[scale=0.3]{img/hardwarecategories}
\caption{General hardware architectures}
\label{fig:HardwareArchitectureCategories}
\end{figure}

Comparing these hardware architecture categories, it is interesting to note that each one represents a different choice in the tradeoff between flexibility and performance. ASICs are highly optimized for their target application, resulting in high performance. However, this optimization comes at the price of a limited function set. On the other end of the spectrum, general purpose processors are powerful because they can perform any reasonable calcuation. Of course, these devices are not nearly as fast or efficient as ASICs. The flexibility/performance tradeoff is an important concept in computer architecture design. Figure \ref{fig:HardwareArchitectureCategories} shows this relationship in a graphical presentation.

\begin{figure}
\centering
\includegraphics[scale=0.3]{img/reconfigurablecategories}
\caption{Reconfigurable hardware architectures}
\label{fig:ReconfigurableHardware}
\end{figure}

Each hardware architecture category can be divided into several subcategories. For the purposes of this discussion, the subcategories of the reconfigurable hardware realm will be examined more closely. They include: field-programmable gate arrays (FPGAs), FPGAs for DSP, and coarse-grain cell arrays.

FPGAs are devices that allow reconfiguration at the lowest possible level. Designers can specify exactly how each bit of their system behaves. While this allows complete control, it also requires significant amounts of work for applications of a significant size.

FPGAs for DSP still allow bitwise control, but they provide shortcuts to developers wishing to implement algorithms for digital signal processing. Usually, these devices will include one or more static, dedicated multipliers for the designer to incorporate into their system. These peripheral components speed up both the design process and the final product, at the cost of a little freedom.

Coarse-grain cell arrays are groups of small functional units that can act together to form a system. The functional units typically implement addition, multiplication, bit shifting, and other simple computations. They usually work with 32 or 64 bits of data at a time, giving them the power to quickly perform large, complex computations.

\subsection{The HiPerCopS Architecture}

The HiPerCopS architecture falls into the reconfigurable hardware category, but it does not necessarily belong to any of the previously established subcategories. This new architecture provides more abstraction than an FPGA for DSP, but it works with smaller data chunks than a coarse-grain cell array. The HiPerCopS architecture is actually a member of a fourth type of reconfigurable devices - the medium-grain reconfigurable hardware architecture \cite{delgado_css03}.

The term `medium-grain' indicates that the architecture works with data that is divided into 4-, 8-, or 16-bit chunks. This increases the amount of control a system designer has over their implementation, but it also allows them to avoid repetitive tasks that are common in FPGAs. This type of architecture represents a reasonable compromise in the tradeoff between flexibility and performance, as shown in Figure \ref{fig:ReconfigurableHardware}.

\subsubsection{Elements}

\begin{figure}
\centering
\includegraphics[scale=0.3]{img/element}
\caption{An element}
\label{fig:element}
\end{figure}

The atomic unit of the HiPerCopS architecture is the \emph{element}, shown in Figure \ref{fig:cell}. An element is an array of 32 bits, which can be treated as a 32x1 storage unit or a 16x2 look-up table (LUT) \cite{myjak_phd06} \cite{myjak_vlsi03}. Depending on the configuration, this basic building block can perform computations or store data. This is the real power of the HiPerCopS architecture.

An element is said to be in `memory mode' when it is being used as a storage unit. Memory mode elements support read and write operations to allow access to the stored data. Both of these operations require five inputs bits to specify the target address. During a data write, a sixth input bit is used to determine whether a logic high or a logic low value should be written. For a data read, a single output bit returns the value at the given address.

When treated as a LUT, the element is said to be in `math mode.' Math mode elements accept four bits of input and produce two bits of output. The input bits are referred to as $\alpha$, $\beta$, $\gamma$, and $\delta$ and the output bits are $\psi_{1:0}$. In most cases, a math mode element uses the inputs and outputs to define a multiply-accumulate (MAC) function, shown in Equation \ref{eq:macelement}.

\begin{equation} \label{eq:macelement}
\psi_{1:0} = \alpha * \beta + \gamma + \delta
\end{equation}

Variations on the MAC can be used to implement a number of different arithmetic computations. For instance, to perform addition alone, $\alpha$ and $\beta$ can be ignored as inputs. To multiply two negative numbers, $\alpha$ and $\beta$ are negated while $\gamma$ and $\delta$ are ignored. From an implementation standpoint, the four inputs represent the address of a LUT row and the output bits are found in the contents of that row. By changing row contents, any bitwise mathematical or logical functions can be implemented.

\subsubsection{Cells}

\begin{figure}
\centering
\includegraphics[scale=0.3]{img/cell}
\caption{A cell}
\label{fig:cell}
\end{figure}

A $4 \times 4$ array of elements is called a \emph{cell}, and cells are the basic building blocks of the HiPerCopS architecture. This grouping of elements abstracts the architecture away from fine-grain issues and elevates it to the medium-grain realm. As with elements, cells can be used in either memory mode or math mode.

Memory mode cells can store $128 \times 4$ bits, or 64 bytes of data. In this mode, seven input bits are used to select the target row. An eigth input bit indicates whether a read or a write operation should be performed. A four-bit data bus is used to provide the inputs for a write or accept the outputs of a read.

By configuring its 16 LUTs in different ways, a cell in math mode can perform mathematical and logical operations with 4-bit granularity. Again, MAC operations are very useful in this context (Equation \ref{eq:maccell}).

\begin{equation} \label{eq:maccell}
y_{7:0} = a_{3:0} * b_{3:0} + c_{3:0} + d_{3:0}
\end{equation}

The elements within a math mode cell must communicate with each other, so they are connected with a set of data busses \cite{myjak_circuits07}. The $a$ and $b$ inputs are broadcasted to every element their respective rows and columns. The $c$ and $d$ inputs are applied to the top row of the cell's elements, and the outputs are produced along the bottom rows and rightmost column, as shown in Figure \ref{fig:elementinterconnect}.

\begin{figure}
\centering
\includegraphics[scale=0.2]{img/elementinterconnect}
\caption{Element interconnect routing within a cell}
\label{fig:elementinterconnect}
\end{figure}

Within a cell, the routing of data from element to element follows a consistent pattern. The inputs propogate through the cell until the longest possible path has been followed. As a result, there is a constant delay between the application of the inputs and the availability of the outputs. In this architecture, the system cycle time is set to compensate for this inner-cell delay. As a result, cell computations complete in a single cycle.

\subsubsection{Cellfields}

\begin{figure}
\centering
\includegraphics[scale=0.3]{img/cellfield}
\caption{A cellfield}
\label{fig:cellfield}
\end{figure}

Although a single cell can perform an impressive number of functions, it does not have the ability to implement complex applications on its own. In order to be useful, most cells need to be part of a larger system. Such a group of cells is called a \emph{cellfield}.

In the most general case, the set of all reconfigurable cells on a piece of hardware can be considered a cellfield. Each of these cells has the ability to perform computations, store and retrieve data, and communicate with its neighbors. The term \emph{device} is used to describe this general cellfield.

Usually, a cellfield is designed to perform a specific function or process. These types of cellfields are called \emph{modules}. Module operations are often simple, involving fewer than forty cells. Since they are relatively small, a number of modules can be implemented on a single device. An application that utilizes multiple modules, routing the outputs of one module to the inputs of another, are called \emph{systems}. The system is the highest level of abstraction in the HiPerCopS architecture.

Inter-cell data communication within a cellfield is not standardized like the inter-element routing within a cell. Every cell in a cellfield has access to two networks: a local mesh and a global H-tree. The local mesh allows the cell to communicate with its adjacent neighbors. This is how modules perform their operations. The H-tree network is the interstate highway system of the HiPerCopS network. It is most useful for inter-module communication within a system \cite{widjaja_circuits05}.

